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BEGIN:VCALENDAR
VERSION:2.0
METHOD:PUBLISH
CALSCALE:GREGORIAN
PRODID:-//WordPress - MECv6.5.5//EN
X-ORIGINAL-URL:https://oursymposium.sites.unlv.edu/
X-WR-CALNAME:Office of Undergraduate Research (OUR) Fall 2021 Virtual Undergraduate Research Symposium
X-WR-CALDESC:
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-PUBLISHED-TTL:PT1H
X-MS-OLK-FORCEINSPECTOROPEN:TRUE
BEGIN:VEVENT
CLASS:PUBLIC
DTSTART;TZID=UTC:20211115T000000
DTEND;TZID=UTC:20211120T000000
DTSTAMP:20211110T000000
UID:MEC-0ebf197205c00fc6e0aac7261a8c1bdc@oursymposium.sites.unlv.edu
CREATED:20211110
LAST-MODIFIED:20211111
PRIORITY:5
TRANSP:OPAQUE
SUMMARY:HNSE-P1-7. Deep Learning on Field Programmable Gate Array
DESCRIPTION:\n\n\nDatino Dixon1\nRobert Lonasco1\nFaculty Mentors: Venkatesan Muthukumar, Ph.D.1 and Sarah Harris, Ph.D.1\n1Howard R. Hughes College of Engineering, Department of Electrical and Computer Engineering\nABSTRACT\nField Programmable Gate Arrays (FPGAs) are a great candidate for implementing deep learning solutions with a focus on enhanced speed and size, due to their lower latency and minimal power consumption. This research aims to further elaborate on DL on FPGA boards due to the versatile architecture of the FPGA. The model FPGA board used for this project was A Xilinx PYNQ z2 as Xilinx offers vast repositories of DL resources which is helpful for exploring the benefits of performing DL on the FPGA. These tools include juptyer interface, python coding compatibility, and ease of cost. To implement deep Learning on the PYNQ z2 board, juptyer notebook was used to install virtual climates and download tools. Then code was implemented and weights were set. After testing different packages a image repository was used with 1000 images and was ran through the code. The research resulted in successful runs of AI guessing images based on a small pool of 1000 images. The research shows deep learning using FPGA boards is achievable and could be further improved.\nThis research was funded by the Southern Nevada Northern Arizona (SNNA) Louis Stokes Alliance for Minority Participation (LSAMP), which is housed within UNLV’s Center for Academic Enrichment and Outreach and supported by a grant (HRD – 1712523) from the National Science Foundation (NSF). Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the NSF. \n
URL:https://oursymposium.sites.unlv.edu/program/deep-learning-on-field-programmable-gate-array/
ORGANIZER;CN=The Office of Undergraduate Research:MAILTO:our@unlv.edu
CATEGORIES:Health & Natural Sciences & Engineering
END:VEVENT
END:VCALENDAR