HNSE-P1-8. Deep Learning on a Xilinx Kria KV260 Vision AI Field-Programmable Gate Array Platform


Robert Lonasco1
Datino Dixon1
Sarah Harris, Ph.D.1
Faculty Mentor: Venkatesan Muthukumar, Ph.D.1
1Howard R. Hughes College of Engineering, Department of Electrical and Computer Engineering

ABSTRACT
Deep Learning (DL) has revolutionized research and development over the past ten years. Several challenges are that DL requires large power consumption and can be slow. Field Programmable Gate Arrays (FPGAs) are great candidates for implementing DL algorithms and solutions because they are configurable and offer low latency and low power consumption. In addition, the FPGA platform has on-chip memory and computation accelerators, for example adders, which decrease memory bottlenecks and helps to prevent memory and bandwidth issues. Furthermore, due to the versatile architecture of the FPGA, users can design application-specific hardware, instead of using general-purpose hardware found in a processor. The Xilinx Kria KV260 Vision AI (KV260) FPGA board was used for this project as it contains numerous accelerated applications for performing DL with a live camera feed. Three major DL solutions were used: Facial Recognition (FR), Figure Detection (FD), and Object Identification (OI). Overall, FR and FD performed well, but OI currently demonstrated low accuracy. Each DL solution had ten test cases with FR, FD, and OI having 90%, 82%, and 57% respectively. These results show that the KV260 can successfully implement a variety of DL solutions, especially as an edge device. A future implementation is to improve upon the current DL training models to provide better accuracy.

Date

Nov 15 - 19 2021
Expired!

Time

All Day

Labels

HNSE: Poster Session 1
The Office of Undergraduate Research

Organizer

The Office of Undergraduate Research
Phone
702-895-4771
Email
our@unlv.edu
Website
http://unlv.edu/our

Speakers

One Reply to “HNSE-P1-8. Deep Learning on a Xilinx Kria KV260 Vision AI Field-Programmable Gate Array Platform”

  1. Hi everyone!
    Thank you for checking out my presentation on deep learning on an FPGA board, it means a lot to me!
    Please feel free to ask away with any questions you may have, along with any feedback or suggestions.
    Thank you!

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