HNSE-P1-7. Deep Learning on Field Programmable Gate Array


Datino Dixon1
Robert Lonasco1
Faculty Mentors: Venkatesan Muthukumar, Ph.D.1 and Sarah Harris, Ph.D.1
1Howard R. Hughes College of Engineering, Department of Electrical and Computer Engineering

ABSTRACT
Field Programmable Gate Arrays (FPGAs) are a great candidate for implementing deep learning solutions with a focus on enhanced speed and size, due to their lower latency and minimal power consumption. This research aims to further elaborate on DL on FPGA boards due to the versatile architecture of the FPGA. The model FPGA board used for this project was A Xilinx PYNQ z2 as Xilinx offers vast repositories of DL resources which is helpful for exploring the benefits of performing DL on the FPGA. These tools include juptyer interface, python coding compatibility, and ease of cost. To implement deep Learning on the PYNQ z2 board, juptyer notebook was used to install virtual climates and download tools. Then code was implemented and weights were set. After testing different packages a image repository was used with 1000 images and was ran through the code. The research resulted in successful runs of AI guessing images based on a small pool of 1000 images. The research shows deep learning using FPGA boards is achievable and could be further improved.

This research was funded by the Southern Nevada Northern Arizona (SNNA) Louis Stokes Alliance for Minority Participation (LSAMP), which is housed within UNLV’s Center for Academic Enrichment and Outreach and supported by a grant (HRD – 1712523) from the National Science Foundation (NSF). Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the NSF. 

Date

Nov 15 - 19 2021
Expired!

Time

All Day

Labels

HNSE: Poster Session 1
The Office of Undergraduate Research

Organizer

The Office of Undergraduate Research
Phone
702-895-4771
Email
our@unlv.edu
Website
http://unlv.edu/our

Speakers

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